Design and implementation of the hottest flicker s

Design and implementation of flicker signal circuit

o introduction

with the development of China's national economy, the power load has increased sharply, especially the proportion of impulsive and nonlinear loads has been increasing, which makes the voltage fluctuate and flicker, and seriously affects the power quality of electricity. Therefore, studying voltage fluctuation and flicker and actively taking measures to ensure power quality have become an important and urgent task for the current power supply department. However, how to get flicker signal becomes an important problem. Therefore, the research of standard flicker signal circuit is an important content of voltage fluctuation and flicker detection and analysis based on SOPC

this paper presents a flicker signal circuit with full digital technology, mainly studies the principle and key parameter design criteria of the circuit, and gives the test results

1 composition and principle of flicker signal circuit

1.1 circuit composition

flicker signal circuit consists of electric voltage sampling and sine wave square wave conversion circuit, frequency doubling circuit or frequency division circuit, clock signal forming circuit (including phase-locked loop and frequency division circuit), phase synchronization circuit (i.e. "single yinmu said address generator zeroing signal forming circuit) The flicker signal generation circuit (including EPROM, D/a conversion circuit and operational amplifier) is composed of five parts, as shown in Figure 1. Its basic idea is to transform the electric voltage UI into a voltage square wave signal, divide the voltage square wave signal (such as n=4) to obtain the reference voltage square wave signal (the frequency is 12.5 Hz), and input it to the phase-locked loop. The output signal of the phase-locked loop is sent back to the phase-locked loop after passing the m frequency division circuit (such as M = 1024) as the comparison signal of the reference voltage square wave signal. When the PLL is in the locked state, the PLL outputs a clock signal whose frequency is m times the square wave signal of the reference voltage. The clock signal is sent to the address generator, and then the digital standard flicker signal solidified in EPROM is read in turn, and then transformed into flicker signal voltage through D/a conversion and operational amplifier

1.2 circuit principle

the main circuit of flicker signal circuit is shown in Figure 2

the electric voltage sampling and sine wave square wave conversion circuit is composed of transformer sampling and zero crossing comparator, and its output voltage square wave signal is synchronized with the electric voltage

the phase synchronization circuit is the formation circuit of 4040 clear signal, as shown in Figure 2 (a). The reference square wave voltage signal is sent to the D trigger 40175 for frequency division, and the 6.25 Hz square wave affecting the working efficiency is output (to ensure that the zero clearing signal is generated once a week), and then its signal and its inverted signal after passing through the non gate 4096 are sent to the monostable trigger 4528, and the zero clearing signal of 4040 is obtained after passing through the OR gate 4071, so as to realize the 1024 frequency division count of 4040, so as to ensure the correct reading of data in EPROM

wave signal into the phase-locked loop, and the phase-locked loop outputs the clock signal required by the circuit. In the locked state of the PLL, the frequency of the clock signal is 1024 times that of the square wave signal of the reference voltage. The clock signal is divided into 1024 frequencies by the frequency divider 4040, and the resulting signal is used as the comparison signal of the phase-locked loop. Send this clock signal to address generator 4040

the flicker signal generation circuit is composed of address generator 4040, eprom27c256, DAC0832 and OP07, as shown in Figure 2 (c). Its core is eprom27c256 and DAC0832. The flicker signal of one cycle can be programmed by MATLAB in advance, and then 1024 frequency division discrete sampling is carried out by MATLAB. After calculating its amplitude, it is arranged into a data table in sequence and stored in EPROM

the clock signal output by the PLL is input to the address generator 40404040, and the data table stored in EPROM is scanned in sequence. The 8-bit binary number representing the amplitude of the flicker signal is sent to DAC0832 to convert the digital quantity into analog quantity output. A series of step flicker waveforms are generated over and over again. Because DAC0832 is a current type device, it must be connected with an operational amplifier to form a D/a converter

2 design of key circuit parameters

phase locked loop CD4046 is one of the key components of the whole pair of high temperature circuits. Its locking range is closely related to the peripheral resistors R4, R5 and capacitor C2. R3 and C1 constitute the external low-pass filter of PLL CD4046

2.1 design of CD4046 external resistors R4, R5 and external capacitor C2

when R5 compensation is not required, that is, R5 is infinite, the output frequency range of the PLL is from zero to the highest output frequency fomax, and:

at this time, fomin=o. In a specific use state, if you want to limit the output frequency range of the PLL, you can realize it through the compensation of R5. The estimation formula of PLL output frequency fo is:

, where: the amplitude of V1 is proportional to the phase difference between the standard voltage square wave signal and the PLL comparison signal; VGS and VTP are the gate source voltage drop of MOS tube inside the PLL respectively; VD refers to the working voltage of PLL. Because this circuit requires the output frequency of PLL to be 12.5 Hz after 1024 frequency division, that is, the PLL must be locked near 12.8 kHz, so r4=10 K, r5=, c2=5.6 NF can be taken

2.2 design of CD4046 low-pass filter R3 and Cl

proper selection of R3 and C1 plays a great role in improving loop capture performance and working stability. If the time constants R3 and C1 are larger, the fatigue testing machine with fast loop tracking will have many advantages, and excessive delay will be caused when entering the frequency; If the smaller time constants R3 and C1 are taken, the loop will track the rapidly changing input signal. Cause abnormal change of PLL output frequency. Considering comprehensively, r3=100 K and c1=2 f are selected

3 experimental results

design example of flicker signal circuit: input voltage =220 V 1o%50 Hz, output standard voltage =0 ~ 15 V (peak) 50 Hz, PLL chip CD4046, address generator 4040, eprom27c256, D/a conversion chip DAC0832, frequency divider 4040, monostable trigger 4528, c1=2 F, c2=5.6 NF, r4=10 K, r5=, r3=100 K, r10=10 K, r9=r11=20 K. The test results of the flicker signal circuit designed and developed are shown in Figure 3

as can be seen from Figure 3, this flicker signal circuit has the advantages of small thd, adjustable amplitude, simple and practical, low price and so on. The experimental results are consistent with the theoretical analysis

4 conclusion

flicker, as an important index to evaluate power quality, can reflect the power supply quality of electricity more directly and quickly. The accuracy of flicker meter is also a matter of concern. In this paper, the theory and type selection of flicker signal circuit are analyzed, and the theoretical flicker signal is realized, which provides a good signal source for the later verification of power quality detection device. The experimental conclusions are as follows:

(1) the flicker signal circuit is composed of five parts: electric voltage sampling and sine wave square wave conversion circuit, frequency doubling or division circuit, clock signal generation circuit, phase synchronization circuit, sine wave generation circuit, etc

(2) the flicker signal circuit has the advantages of small thd, adjustable amplitude, simple and practical, low price and so on

(3) the test results are consistent with the theoretical analysis