Design and implementation of radar simulation sign

The design and implementation of radar simulation signal based on CPLD

Introduction

with a large number of new generation combat aircraft being in service, the maintenance task of airborne radar equipment is becoming more and more heavy, and the modern simulation and test system has become an important maintenance equipment. The simulation of radar signal is also essential in the test system. However, using function/arbitrary wave generator to form a test system not only increases the cost of the system, but also adds unnecessary burden to the system software design. Therefore, an implementation scheme of radar simulation signal based on CPLD is proposed, which can provide a variety of typical PRF pulses and guidance signals for airborne radar test system

structure of radar simulation signal generator

radar simulation signal generator is mainly composed of input and output control and CPLD chip that generates simulation signal. The input and output control signal is generated by the industrial computer of the test system through the digital i/o card. When the industrial computer outputs a valid signal through the digital i/o card, the so-called "partner" of the generator will output the corresponding pulse signal. The structure of radar simulation signal generator is shown in Figure 1

Figure 1 Structure of radar simulation signal generator

in the figure, the control signals of radar simulation signal generator include radar simulation signal pulse switch, joint signal United switch, guidance signal sa-h switch, guidance signal sa-l switch and irradiation output sa-w switch. The above switches are effective at low level. When the "pulse switch" is effective, the radar simulation signal generator is in working state. At this time, as long as any control signal is effective, it can output the corresponding radar simulation signal. When "sa-h" is valid, "out1" outputs high repetition frequency pulse signal; When "sa-l" is valid, "out1" outputs PRF pulse signal; When "sa-w" is valid, "out2" outputs irradiation pulse signal; When "united" is effective, "O Sandvik material technology is a world leading developer and manufacturer of advanced stainless steel and special alloy products for the most severe environment. UT3" outputs the combined pulse to lay a foundation for the plastic processing industry to enter the ranks of the world's advanced countries, that is, add high repetition frequency or medium repetition frequency pulse signals at the bottom level of the irradiation pulse

cpld internal circuit design and simulation

the CPLD selected in this design is epm7128slc84 of Altera company, which belongs to MAX7000 series. MAX7000 series provides 600 ~ 5000 usable gates (1200 ~ 10000 gates are provided on the device), the pin to pin delay is 6ns, and the counter frequency can reach 151.5mhz

cpld is the core of radar simulation signal generator. Its internal circuit is mainly divided into 6 sub modules, including 5 frequency division and pulse width shaping module, 10 frequency division and pulse width shaping module, 60 frequency division and pulse width shaping module, 100 frequency division circuit, 625 frequency division circuit and pulse output selector. The connection relationship between modules is shown in Figure 2

Figure 2 connection relationship between modules inside CPLD

clock pulse input CLK frequency provides 10MHz signal for external crystal oscillator, and provides 50ns pulse width input signal for 10 frequency division and pulse width shaping circuit, 60 frequency division and pulse width shaping circuit, and 100 frequency division circuit. The 100 frequency division and 625 frequency division circuits are designed with the macro function lpm-counter (preset counter) of max+plus Ⅱ. The 10MHz signal is input by the CLK end of lpm-counter, and cout is the pulse output end after frequency division. Set the function modulus and width parameters according to the required pulse frequency. Take the 100 frequency division circuit as an example, set modulus to 100, and the corresponding width is set to 7. When the macro function control signals are set to the counting state, Start counting when the rising edge of CLK comes. When the count reaches 100, the counter returns to zero and outputs a pulse with a pulse width of CLK clock cycle in cout, which is repeated so as to achieve the purpose of 100 frequency division. Fig. 3 shows the simulation waveform of 100 frequency division

Figure 3 simulation waveform of 100 frequency division

60 frequency division and pulse width shaping circuit generation cycle 6 μ s. Pulse width 1.2 μ S, and its structure is shown in Figure 4. The frequency division circuit adopts the same design method as above. Only set the module and width parameters to 60 and 6 respectively, that is, the generation period is 6 μ S pulse with a pulse width of 100ns (CLK 100ns in Figure 5). Take this signal as the clock signal of the D flip-flop, and the input end of the D flip-flop always maintains the high level, so that when the D flip-flop arrives at the rising edge of the clock, the output will always maintain "1", but in order to get 1.2 μ S pulse width must be 1.2 μ Reset D trigger after s. The design of the reset signal also uses the lpm-counter function. The input signal of the function is a 10MHz pulse signal, and the parameters of module and width are set to 13 and 4 respectively. When the count reaches 13 (the 13th rising edge appears at the CLK input, and the last 12 cycles of the real-time clock are 1.2 μ s) Count control navigation, information entertainment and other in car communication system devices to zero and generate pulses in cout. Connect D trigger (d:clrn in Figure 5) through the inverter to reset the trigger end to reset it to output "0". In order to make the counter not in the counting state when the D trigger outputs "0"